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? Conversion of PDB file to STAPL has finish and created *.stp file can be used for
programming Actel device.
Frequently asked questions about Actel
Q: How can be identify/verify already programmed Actel device?
A: There are several possible options to get this done. Each option(action) is varying from
each other in method of comparing already programmed Actel device with loaded STAPL
file. There are the following appropriate mentioned actions in a STP file:
DEVICE_INFO: read and among other things display to log window also the checksum of
the programming environment programmed into the device. This value can be manually
compared by user with the value in the header of the STAPL file (can be viewed in
Information window). Caution: Value of the programmed device checksum isn't counting
from existing(maybe corrupted) device data content however this value is stored during
programming to special memory localization and is only reading!
VERIFY_DEVICE_INFO: similar options as previous with difference in automatic
comparison of programmed device checksum and STAPLE file checksum. The result of
comparison can be either success or error window message.
VERIFY: the safest but the slowest(~tens of seconds depends on device capacity against
~1 second in options 1 and 2) option for data compare programmed device content with
content of STAPLE file. Comparison selected family features(FPGA Array, targeted
FlashROM pages, security setting...) is executing bit by bit and verification process can be
early terminated if data mismatch occurs with writing error message to log window.
Q: Is it possible to program Actel device with two different STAPLE file in one program action
in PG4UW?
A: Yes, it is possible. PG4UW control program has built-in multi-project solution for
mentioned situation. As an example can be programming data content (first STAPL file)
together with security encryption key(second STAPL file).
The IspVM Virtual Machine
The IspVM Virtual Machine is a Virtual Machine that has been optimized specifically for
programming devices which are compatible with the IEEE 1149.1 Standard for Boundary
Scan Test. The IspVM EMBEDDED tool combines the power of Lattice's IspVM Virtual
MachineTM with the industry-standard Serial Vector Format (SVF) language for Boundary
Scan programming and test.
The IspVM System software generates VME files supporting both ispJTAG and non-Lattice
JTAG files which are compliant to the IEEE 1149.1 standard and support SVF or IEEE 1532
formats. The VME file is a hex coded file that takes the chain information from the IspVM
System window. The devices can be programmed in ZIF socket of the programmer or in
target system through ISP connector. It is indicated by [PLCC44](VME) or (ISP-VME) suffix
after name of selected device in control program. Multiple devices are possible to program
and test via JTAG chain: JTAG chain (ISP-VME).
More information on the website: http://www.latticesemi.com
Software tools:
Lattice: ispLEVER, IspVM System ISP Programming Software, PAC-Designer Software,
svf2vme utility (converts a serial vector file to a VME file)
Device / Device info
The command provides additional information about the current device - size of device,
organization, programming algorithm and a list of programmers (including auxiliary modules)
that supported this device. You can find here package information, part number description
95
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